1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to enhancing heat dissipation in semiconductor devices by providing a back side metallization.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are continuously decreased with the introduction of every new circuit generation to provide currently available integrated circuits formed by volume production techniques with critical dimensions of 50 nm or less and having an improved degree of performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs (central processing units), GPUs (graphical processing units) and the like. The reduction in size is commonly associated with an increased switching speed, thereby enhancing signal processing performance at transistor level. Due to the decreased dimensions of the active circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC).
As the number of circuit elements, such as transistors and the like, per unit area increases in the device level of sophisticated semiconductor devices, the number of electrical connections associated with the circuit elements in the device level also has to be increased, typically even in an over-proportional manner, thereby requiring complex interconnect structures which may be provided in the form of metallization systems including a plurality of stacked metallization layers. In these metallization layers, metal lines providing the inner level electrical connections and vias providing intra level connections are formed on the basis of very conductive metals, such as aluminum, copper and the like, in combination with appropriate dielectric materials to reduce the parasitic RC (resistance capacitance) time constants. Generally, in semiconductor devices requiring a complex contact regime for connecting the metallization system with the device periphery, i.e., with a package substrate and the like, frequently, a bump structure is provided as the very last layer of the metallization system in which contact bumps, such as solder bumps or any other type of metal elements, such as pillars and the like, are provided in the passivation material of the semiconductor chip in order to act as contact areas for connecting to complementary contact elements of a package substrate and the like. For instance, solder material may be provided on at least one of the contact elements of the semiconductor chip and the substrate package, which may be subsequently re-flowed after mechanically contacting these two components. In this manner, an electrical and mechanical contact may be established between the semiconductor chip and the carrier substrate with high electrical performance due to a reduced contact resistance and a reduced parasitic capacitance. In this contact technology, the entire available chip area may be used for positioning individual bumps or metal elements without being restricted to the periphery chip area, as may be the case in well-established wire bonding techniques. Due to the increasing complexity of sophisticated semiconductor devices, typically, the input/output (I/O) capabilities and thus the number of bumps or metal elements in the bump structure also has to be increased, wherein, however, the requirement for an increased packing density in the device level and in the metallization system may also result in an increased packing density of metal elements in the bump structure. For example, in semiconductor devices including circuit elements including critical dimensions of 30 nm and less, a typical pitch between neighboring bumps may be approximately 180 μm with the prospect of pitches of 165-130 μm in further advanced device generations.
As previously explained, the high packing density typically in the device level, i.e., in the semiconductor material of the semiconductor device, typically results in an increased power consumption, as, for instance, the static and dynamic power consumption of very sophisticated transistor elements may increase, for instance due to a reduced thickness of gate dielectrics and the like, while, in other cases, in addition to the increased power consumption of individual transistors, the increased packing density may finally result in an increased power consumption per unit area, which in turn leads to the generation of an increased amount of waste heat. One path of dissipating heat from the semiconductor level to the periphery is heat conductivity via the metallization system and the bump structure into the substrate carrier, which in turn may be coupled to any appropriate heat sink arrangement. Due to the increased number of metallization levels in the metallization system of very complex semiconductor devices and due to the fact that increasingly dielectric materials of reduced dielectric constant are used in the metallization systems, the thermal resistance of the metallization system including the bump structure may no longer be compatible with the heat dissipation capabilities required in sophisticated applications. For this reason, frequently, the substrate back side of semiconductor devices may also be used as an efficient heat dissipation path, which may be connected to the periphery, for instance a package and the like, by an appropriate thermal interfacial material that thermally connects the substrate back side to the package substrate. For example, indium is frequently used as a thermal interfacial material due to its superior heat conductivity. In other cases, gallium, silver, copper and the like may also be efficiently used as a thermal interfacial material. Due to the material characteristics, such as diffusion behavior, adhesion with specific materials such as silicon and the like, the thermal interfacial material may typically not be directly formed on the substrate back side, such as a silicon surface, but may require additional material layers in order to obtain the desired thermal, mechanical or chemical behavior of the coupling between the substrate back side and a package. For this purpose, an adhesion layer is formed on the surface of the substrate in order to provide adhesion of the following materials to the semiconductor material of the substrate. For instance, aluminum, aluminum alloys, titanium, titanium nitride, tantalum, tantalum nitride, tantalum silicide are materials frequently used as an adhesion material. Thereafter, a barrier material, such as titanium, tantalum, tantalum nitride, tantalum silicide, nickel, chromium and the like, is provided in order to prevent the diffusion of indium, i.e., of the thermal interfacial material, into the material of the substrate, such as silicon and the like. In addition to these material layers, one or more layers are also provided to act as an adhesion layer appropriately attaching the thermal interfacial material to the back side metallization stack and thus to the semiconductor substrate. For this purpose, materials consisting of gold, gold alloys, platinum, gold/platinum alloys, copper, silver and the like may be used. Consequently, a moderately complex metallization layer stack is to be formed on the back side of the semiconductor substrate, in which a plurality of different materials have to be deposited, at least some of which may typically have a negative effect on the semiconductor devices and process techniques so that, in view of the prevention of any cross-contamination, the back side metallization layer stack is typically provided in a very advanced manufacturing stage, i.e., the back side metallization layer stack is formed at one of the last process steps in a semiconductor facility. It turns out, however, that the back side metallization stack may result in significant yield loss during the further processing of the semiconductor devices, in particular when a reduced pitch of a bump structure is required, as will be explained with reference to FIG. 1.
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100 which comprises a substrate 101, such as a silicon substrate, a silicon-on-insulator (SOI) substrate and the like. As previously discussed, the substrate 101 may act as a carrier for forming therein and thereon circuit elements, such as field effect transistors, capacitors, resistors and the like, as are required for providing a complex integrated circuit. For example, the substrate 101 comprises a semiconductor layer 110, which may also be referred to as a device level, in and above which are provided a plurality of circuit elements (not shown) which may generate a significant amount of heat, as indicated by 110A. As discussed above, the packing density and the configuration of individual circuit elements may have a significant influence on the heat generation in the device level 110. For example, in sophisticated applications, transistor elements, such as field effect transistors, having a short channel in combination with a very thin gate dielectric material may exhibit an increased static power consumption, for instance due to leakage currents through a very thin gate dielectric material. Moreover, in digital circuits, the operating frequency is typically selected at several hundred MHz up to several GHz, thereby also contributing to significant dynamic losses in the form of high transient currents so that a very efficient heat dissipation is required in order to meet the specifications of sophisticated semiconductor devices. Moreover, the device 100 comprises a metallization system 120, which is to be understood as a plurality of individual metallization layers (not shown) that provide the network of electrical connections between the individual circuit elements in the device level 110. It should be appreciated that circuit elements may also be provided in the metallization system 120 and in the substrate 101 below the device level 110, for instance in the form of capacitors and the like, depending on the overall complexity and configuration of the device 100. For convenience, any such circuit elements are not shown in FIG. 1.
Furthermore, a bump structure 130 is provided on and above the metallization system 120 and represents a plurality of bumps 132, at least many of which are electrically connected to the metallization system 120, thereby providing the I/O capabilities of the device 100 for communication with the periphery, for instance in the form of a package substrate and the like. The bump structure 130 may comprise any appropriate dielectric material 131 for passivating the device 100, while the bumps 132, which may also be provided in the form of metal pillars and the like, are comprised of any appropriate metal material, such as solder material and the like. As previously explained, a pitch between neighboring bumps 132 may be 180 μm for sophisticated semiconductor devices and may have to be significantly reduced in even more complex semiconductor devices.
Moreover, at a back side 101B of the substrate 101, a metallization layer stack 140 is formed in order to allow the attachment of an appropriate thermal interfacial material, such as indium, in a later manufacturing stage. The layer stack 140 comprises an adhesion layer 141, such as an aluminum layer or a layer comprised of one of the materials mentioned above, with an appropriate thickness of, for instance, approximately 100 nm. The adhesion layer 141 is to provide desired high adhesion of the subsequent materials of the layer stack 140 and of the indium material to be provided in a further advanced manufacturing stage. Furthermore, a barrier layer 142, such as a titanium layer, having a thickness of approximately 100 nm is formed on the adhesion layer 141. Furthermore, a further metal-containing material, for instance in the form of nickel vanadium (NiV) 143, is formed on the barrier material 142 with any appropriate thickness, such as approximately 350 nm. Finally, the layer stack 140 comprises a further metal layer 144, such as a gold layer, which may be considered as an adhesion layer for ensuring a desired high degree of adhesion with respect to the thermal interfacial material, such as indium, to be formed on the layer 144 at a later stage. The layer 144 may be provided with a thickness of approximately 100 nm.
The semiconductor device 100 as illustrated in FIG. 1 may be formed on the basis of the following processes. The semiconductor layer 110 may be appropriately processed in order to form circuit elements therein and thereabove, for instance by providing isolation structures (not shown) to divide the semiconductor layer 110 into appropriate semiconductor regions. Thereafter, the circuit elements in the form of transistors, resistors, capacitors and the like are formed in and above the semiconductor regions and above isolation structures, depending on the overall configuration of the device 100. As indicated above, in sophisticated devices, critical dimensions in the device level 110 may be 50 nm and significantly less. Thereafter, the circuit elements are embedded in a dielectric material (not shown), in which appropriate contact elements are provided to connect the circuit elements with the metallization system 120. Next, the metallization system 120 may be formed by providing a plurality of metallization layers, each of which may include an appropriate dielectric material in combination with metal features, such as metal lines and vias, in accordance with the circuit layout of the device 100. Finally, the bump structure 130 is formed by depositing the dielectric material 131 and patterning the same in order to form appropriate openings for receiving the bumps 132. The bumps 132 may be formed by providing any appropriate “underbump metallization system” (not shown) and depositing any appropriate conductive material, for instance by electrochemical deposition techniques, and finally removing any non-desired excess material.
During the entire process flow, well-established process techniques are used wherein the back side 101B of the substrate 101 may be exposed to various process environments, for instance by handling the device 100, which may typically be accomplished by contacting the substrate 101 at an edge region and/or on the back side 101B, by positioning the substrate 101 on substrate holders of process tools by exposing at least a portion of the back side 101B to the deposition atmosphere of many deposition processes and the like. Consequently, the back side 101B may at least be partially modified with respect to its chemical and mechanical characteristics during the entire process flow for forming the semiconductor device 100 as shown in FIG. 1. Furthermore, in a very advanced manufacturing stage, for instance after forming the bump structure 130, the back side metallization stack 140 is formed in order to avoid the contamination of other device areas of the device 100 and/or the contamination of process tools and the like. For example, a plurality of metal species may result in significant modification of device characteristics when diffusing into sensitive device areas. During the formation of the layer stack 140, typically, the device 100 is positioned in an appropriate process tool for establishing a sputter deposition ambient in order to form the aluminum layer 141 on the back side 101B. For this purpose, any appropriate process chamber, for instance of a cluster tool and the like, may be used in combination with an appropriate target material provided therein by establishing appropriate deposition conditions, such as plasma power for ionizing a carrier gas and to sputter off target atoms from the target material by directing ionized particles to the sputter material. The atoms and/or ions that are released from the target material upon the particle bombardment may then deposit on the surface 101B. Thereafter, the device 100 is positioned in a further sputter deposition chamber in which the titanium material of the layer 142 is deposited on the layer 141. Similarly, the material layer 143 may be provided by sputter deposition in a further sputter deposition chamber having an appropriate target material provided therein. Finally, the gold layer 144 may be formed by sputter deposition in a further sputter deposition chamber on the basis of appropriate process parameters. Consequently, in the example shown in FIG. 1, four sputter deposition tools or process chambers are used for providing the metallization stack 140. During the further processing of the device 100, the substrate 101 is to be separated into individual semiconductor chips, which is accomplished by appropriately dicing the substrate 101, as indicated by 102. During the process 102, the materials of the back side layer stack 140 are also separated, which may result in additional metal-containing contaminating particles 102A, which may also deposit on the bump structure 130. Consequently, these contaminants 102A stemming from the layer stack 140 may cause leakage paths in the bump structure 130 and may even result in a shorting of neighboring bumps 132. Consequently, significant yield loss may be generated in a very advanced manufacturing stage due to the presence of the back side metallization layer stack 140. Furthermore, as previously discussed, upon further reducing the pitch between adjacent bumps 132, the probability of causing yield loss in the bump structure 130 may even further increase. On the other hand, the layer stack 140 may be required for enabling the provision of a thermal interfacial material to be formed on the stack 140 so as to thermally couple the device level 110 to a package substrate when the heat dissipation via the metallization system 120 is not sufficient for meeting the thermal specifications of the device 100. Due to the increased probability of creating contamination during the patterning of the stack 140 during the process 102, it has also been proposed to remove the material of the stack 140 within scribe lanes of the device 100, thereby substantially avoiding the release of any contaminating particles, such as the particles 102A during the process 102. For this purpose, however, additional complex patterning strategies, such as lithography and etch processes, are required in a very advanced manufacturing stage thereby significantly contributing to increased production costs for sophisticated semiconductor devices.
In view of the situation described above, the present disclosure relates to semiconductor devices and manufacturing techniques in which a back side metallization layer stack may be provided while avoiding or at least reducing one or more of the problems identified above.